In this article
How to use this list
Each entry gives a short answer, one line on why interviewers ask it, and, where a listed source covers the topic, a pointer to further reading. Verilog is a hardware description language (HDL), which means it describes circuits that exist in parallel, not instructions that run one after another. Keep that picture in mind and most answers follow from it. Behaviours with numbers were computed in a short script, not recalled.1 For the general method of a coding round, read the coding interview guide; for a software-language list in the same format, see the Python interview questions.
Verilog coding interview questions for freshers: the basics
What is Verilog, and what is the difference between simulation and synthesis?
Verilog is an HDL used to model digital circuits. Simulation executes the code in a tool to show how signals change over time. Synthesis turns a subset of the code into gates and flip-flops. Not everything that simulates can be built: delays and most initial blocks (outside field-programmable gate array (FPGA) register power-up values) are typical examples. Say which subset you are writing.
Why it is asked: it shows whether you know the code is a circuit description. Further reading: Institute of Electrical and Electronics Engineers (IEEE) Std 1364-2005.
What is the difference between wire and reg?
A wire is a connection driven by something else, such as a continuous assign statement or a module output. A reg is a variable that holds a value and is assigned inside always or initial blocks. Despite the name, a reg does not always become a flip-flop: in a combinational block it synthesizes to plain logic. In SystemVerilog, logic removes the confusion: one type works for either kind of signal.
Why it is asked: "reg means register" is a frequent misconception. Further reading: IEEE Std 1364-2005.
What is the difference between = and == and ===?
A single = assigns; == compares and returns x when unknown or z bits make the comparison ambiguous; if the known bits already differ, it returns 0 (IEEE Std 1364-2005, §5.1.8). The === operator compares including x and z bits, so it returns a definite true or false. It is for testbenches, because it is not meaningful in hardware.
Why it is asked: it checks four-valued logic, where a bit can be 0, 1, x or z. Further reading: IEEE Std 1364-2005.
Knowing it is half the job. Saying it is the other half.
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Start Free Trial →Assignments and combinational logic
What is the difference between blocking and nonblocking assignments?
A blocking assignment (=) completes before the next statement runs. A nonblocking assignment (<=) evaluates its right side now and updates the left side at the end of the time step, so statements in the block see old values. The usual guideline is nonblocking in clocked blocks and blocking in combinational ones (Cummings, 2000).
Why it is asked: it is a staple Verilog question. Further reading: Cummings, nonblocking assignments.
How do you swap two registers in one clock edge?
Write a <= b; b <= a; in a clocked block. Both right sides are read before either update, so the values trade places. With starting values 1 and 2, the nonblocking version ends with a equal to 2 and b equal to 1, while blocking = statements in the same order leave both at 2.1
Why it is asked: it makes the scheduling difference concrete. Further reading: Cummings, nonblocking assignments.
What is a latch, and how does Verilog code create one by accident?
A latch is a level-sensitive storage element that holds its value while its enable is off. A synthesis tool infers one when a combinational always block does not assign an output on every path, for example an if with no else or a case with no default. Assign a default value at the top of the block to avoid it.
Why it is asked: unintended latches are a classic real bug.
What goes in the sensitivity list of a combinational always block?
Every signal the block reads. Writing always @(*) lets the tool build the list, which avoids the bug where simulation ignores a signal that the synthesized circuit does depend on. Leaving one out makes simulation and hardware disagree.
Why it is asked: it tests the gap between what simulates and what is built. Further reading: IEEE Std 1364-2005.
How would you write a 4-to-1 multiplexer?
Use a case on the two select bits inside always @(*), assign the output in every branch, and include a default. An alternative is a continuous assignment with the conditional operator, or indexing a vector with the select value. Name the version you prefer and say all of them give the same logic.
Why it is asked: it is a warm-up that checks latch awareness. Further reading: IEEE Std 1364-2005.
Flip-flops, counters and registers
How do you code a D flip-flop with a synchronous or asynchronous reset?
Use always @(posedge clk) with nonblocking assignments. For a synchronous reset, test reset inside the block; it acts only on a clock edge. For an asynchronous reset, add the reset edge to the list, as in always @(posedge clk or negedge rst_n), so reset acts at once. State which one the design needs and why.
Why it is asked: reset style affects timing and recovery behaviour.
How do you write a 4-bit counter, and what happens at the top?
Declare a 4-bit register, reset it to zero and add one on each clock edge with a nonblocking assignment. The register counts through 16 values, 0 to 15, and wraps from 15 back to 0 by itself because the sum is truncated to four bits.1
Why it is asked: it checks width, reset and overflow reasoning. Further reading: IEEE Std 1364-2005.
How do you divide a clock by 2?
Use a flip-flop that inverts its own output on every rising edge of the input clock: q <= ~q;. The output toggles once per input cycle, so its period is two input cycles; over 8 input cycles it has 4 rising edges.1 The register q needs a reset or an initial value, or it simulates as x and never toggles. In real designs, prefer a clock-enable over a derived clock where possible.
Why it is asked: it tests sequential thinking, and the follow-up asks about derived clocks.
How deep is a shift register, and what breaks it?
A three-stage shift register needs three clock edges before a new input reaches the output.1 It works when each stage is assigned with a nonblocking assignment, because every stage reads the old value of the one before. With blocking assignments written from input to output (q1 = d; q2 = q1; q3 = q2;), the input races through all stages in a single edge, so one stage results.1 Written in reverse order, blocking assignments happen to work, which is why order-dependent code is fragile.
Why it is asked: it shows the practical result of the scheduling rule. Further reading: Cummings, nonblocking assignments.
State machines and clocks
What is a finite state machine, and what is the difference between Moore and Mealy?
A finite state machine (FSM) is a circuit with a fixed set of states, a state register and rules for moving between them. In a Moore machine outputs depend only on the current state; in a Mealy machine they also depend on the inputs, so they can react sooner but may glitch. State your choice and why.
Why it is asked: FSMs are a staple of design rounds. Further reading: Cummings, state machine coding styles.
How do you code an FSM cleanly?
Separate the logic: one clocked block for the state register using nonblocking assignments, one combinational block for the next state with a default assignment, and outputs derived from the state. Use named states with localparam, and give case a default branch that returns to a safe state.
Why it is asked: it tests style that avoids latches and race conditions. Further reading: Cummings, state machine coding styles.
How do you write a sequence detector for 1011?
Build an FSM whose states record how much of the pattern has been seen: nothing, 1, 10 and 101, plus a detected output on seeing the final 1. In an overlapping detector, a match returns the machine to the state for 1, because the last bit can start the next match; a non-overlapping detector returns to the start state. On the input stream 1011011, the overlapping detector flags 2 matches and the non-overlapping one flags 1.1 Ask which kind is wanted before you draw the states.
Why it is asked: it combines state design with a precise requirement. Further reading: Cummings, state machine coding styles.
How do you pass a signal between two clock domains?
A single-bit signal goes through a synchronizer. A synchronizer is a chain of two flip-flops in a row in the destination clock domain that gives the first stage time to settle. Metastability is a state in which a flip-flop's output hovers between 0 and 1 because its input changed inside the setup and hold window, the short time around the clock edge when the input must stay steady; the first flip-flop may go metastable, and the second samples it a cycle later, after it has most likely settled.
That adds about two destination clock cycles of latency (modelled as exactly two).1 A multi-bit value must not be copied bit by bit, because bits can arrive on different cycles; use a handshake or an asynchronous first in, first out (FIFO) buffer, or, for a counter that changes by one step at a time, Gray code.
Why it is asked: clock domain crossing (CDC) errors are subtle and costly. Further reading: Cummings, clock domain crossing.
Why is Gray code used for FIFO pointers?
A Gray code is an ordering of binary values in which consecutive values differ in exactly one bit. It is built as g = b ^ (b >> 1). In 3-bit binary, going from 3 to 4 flips three bits, but in Gray code it flips one, including the wrap from 7 back to 0.1 A pointer sampled mid-change in another clock domain is then off by at most one step.
Why it is asked: it links number representation to a hardware failure. Further reading: Cummings, clock domain crossing.
Testing
What is a testbench, and how do you write a simple one?
A testbench is a module with no ports that instantiates the design, drives its inputs and checks its outputs. Set clk = 0 in an initial block, then generate the clock with always #5 clk = ~clk;, which gives a period of 10 time units (without the initial value, clk stays x because ~x is x). Apply reset, drive stimulus in an initial block, compare outputs with expected values and finish. Testbenches may use delays and === because they are never synthesized.
Why it is asked: it shows you verify your own design. Further reading: the University of Maryland, Baltimore County lecture notes on events, timing and testbenches.
Follow-up questions
What are Verilog coding interview questions?
They are short design or reading tasks in which you write or fix a few lines of Verilog and explain the hardware they describe. The eighteen above cover the ones that recur: assignments, latches, flip-flops, counters, state machines and clock crossing.
What are Verilog coding interview questions for freshers?
Freshers are usually asked the basics first: wire against reg, blocking against nonblocking, a flip-flop with reset, a counter, a multiplexer and a simple state machine. Practise writing each from memory and say out loud what hardware it becomes. The first group above is a starting set.
Is Verilog a programming language?
Verilog is a hardware description language. Its statements describe concurrent hardware, not a sequence a processor executes, even though its syntax resembles software. For how software concurrency differs, see parallel processing, and for bit and byte layout questions that overlap with hardware rounds, see little-endian byte order.
How should I practise for a Verilog coding round?
Write each circuit above in a simulator, check the waveform, then explain the circuit in two sentences. Some rounds also include ordinary algorithm problems; the coding interview guide covers that method, and graph questions such as topological sort or cycle detection in a directed graph show the style.
- Use nonblocking assignments in clocked blocks and blocking in combinational blocks.
- Assign every output on every path to avoid an accidental latch.
- A
regis a variable, not always a flip-flop. - Describe a state machine with a state register, a next-state block and a safe default.
- Cross clock domains with a two-flop synchronizer for one bit and Gray code or a handshake for many bits.
Sources
- IEEE Standard for Verilog Hardware Description Language (IEEE Std 1364-2005) — IEEE, 7 Apr 2006
- Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill! (Cummings, SNUG 2000) — Sunburst Design (Cummings), 1 Mar 2000
- State Machine Coding Styles for Synthesis (Cummings, SNUG San Jose 1998) — Sunburst Design (Cummings), 1 Mar 1998
- Clock domain crossing design and verification (Cummings, SNUG 2008) — Sunburst Design (Cummings), 1 Sep 2008
